1. Field of the Invention
The present invention relates to a digital-to-analog (D/A) converter circuit, a liquid crystal driving circuit, and a liquid crystal display apparatus.
2. Description of the Related Art
Nowadays, liquid crystal devices (LCDs) are in wide use as displays. Since such LCDs are thin, light, and low power consumption, they are often used for mobile terminals, such as mobile phones, personal digital assistances (PDAs), notebook computers, and portable televisions.
Large liquid crystal devices have been developed and have been applied to large-screen stationary displays and large screen televisions.
Such a liquid crystal device includes a liquid crystal panel and a liquid-crystal-panel driving circuit that drives the liquid crystal panel. The liquid-crystal-panel driving circuit converts a digital signal input as an image signal into an analog signal at an internal D/A converter circuit and inputs the analog signal to the liquid crystal panel so as to display an image on the liquid crystal panel.
As described above, the liquid-crystal-panel driving circuit includes a D/A converter circuit that converts a digital signal into an analog signal. For such a D/A converter circuit, in the past, a resistive ladder type has mainly been used.
As shown in FIG. 10, with a resistive ladder type D/A converter circuit, a plurality of resistors R101 are connected in serial between reference voltages (between VRT-0 V). Then, a decoder 102 controls a switching unit 101 so as to select a first voltage corresponding to a digital signal among the tap voltage between the resistors R101 and output an analog signal Vout corresponding to the input digital signal.
In this way, a resistive ladder type D/A converter circuit includes a number of resistors equaling the gradation level between the reference voltage. Each resistor is connected to a switching circuit so that a desired resistor tap can be selected. A resistive ladder type D/A converter circuit has been put to wide use because the structure is simple and easy to construct and because it exhibits good performance.
However, recently, along with the increase in image quality of liquid crystal devices, 10 bit or higher gradation level is required for a D/A converter circuit. Therefore, known resistive ladder type D/A converter circuit have been facing their limits.
In other words, with a resistive ladder type D/A converter circuit, since the numbers of resistors R101 and switches SW101 double as the number of bits increase, the mounting area (chip size) also doubles. Usually, about 8 bits is a realistic limit to a resistive ladder type D/A converter circuit due to limitations on the mounting area. Thus, the limit on the relative accuracy of resistors that can be mounted on a semiconductor is set.
Accordingly, recently, attention has been given to a serial cyclic D/A converter circuit whose mounting area does not increase even when the gradation level is increased (for example, refer to Japanese Unexamined Patent Application Publication No. 2001-94426).
Now, the principle of a known cyclic D/A converter circuit will be described with reference to the drawings. FIG. 11 illustrates the principle of a known cyclic D/A converter circuit.
As shown in FIG. 11, a cyclic D/A converter circuit 110 includes a parallel-to-serial converter circuit 111 that converts parallel digital data, which is a digital signal, into serial digital data, a switching unit 112 that outputs a voltage corresponding to each bit of serial digital data output from the parallel-to-serial converter circuit 111, an multiplying unit 113 that multiplies the voltage output from the switching unit 112 and the voltage output from a voltage converter circuit 115, described below, a sample hold (S/H) circuit 114 that holds the voltage output from the multiply unit 113, and the voltage converter circuit 115 that reduces the voltage output from the S/H circuit 114 by half.
The parallel digital data input to the cyclic D/A converter circuit 110 is converted into serial digital data by the parallel-to-serial converter circuit 111 and is output in sequence to the switching unit 112.
The switching unit 112 output in sequence a voltage (a first voltage VRT or a second voltage (zero volts in this case)) corresponding to data of each bit of the serial digital data. For example, when the digital data is “1,” a switch SW101 is short-circuited so as to output the first voltage VRT, whereas when the digital data is “0,” a switch SW102 is short-circuited so as to output the second voltage (zero volts).
The multiplying unit 113 adds the output voltage from the voltage converter circuit 115 to the voltage output in sequence from the switching unit 112, and then outputs the result to the S/H circuit 114.
Then, half of the voltage output from the S/H circuit 114 is output from the voltage converter circuit 115. This voltage is the output voltage Vout from the cyclic D/A converter circuit 110.
In this way, every time a voltage corresponding to bit data is output from the switching unit 112, the cyclic D/A converter circuit 110 adds to this voltage half the voltage held in the S/H circuit 114. By holding the result at the S/H circuit 114 and reducing the voltage by half, the output voltage Vout is generated, and a digital signal is converted into an analog signal.
Next, an example of a detailed structure of a cyclic D/A converter circuit employing the above-described principle will be described with reference to FIG. 12. FIG. 12 illustrates a detailed structure of a cyclic D/A converter circuit.
As shown in FIG. 12, a D/A converter circuit 120 includes a parallel-serial converter circuit 121 that converts parallel digital data into serial digital data, switches SW120 and SW121 that select either a first voltage VRT or a second voltage (zero volts in this case) for each bit of digital data depending on the serial digital data output from the parallel-serial converter circuit 121, a first capacitor C120 that receives the first voltage or the second voltage applied by short-circuiting the switch SW120 or SW121, a switch SW122 that connects the first capacitor C120 and a second capacitor C121 in parallel, described below, the second capacitor C121, switches SW123 and SW124, and a voltage follower AMP120. The first capacitor C120 and the second capacitor C121 have the same capacitance Ca(F).
With the D/A converter circuit 120 configured as described above, for example, when the digital signals Dm-1, Dm-2, . . . D1, and D0 input to the D/A converter circuit 120 correspond to “1111,” the switches SW120 to SW124 and the second capacitor C121 enter states as illustrated in FIG. 13.
First, at a timing t0, the switches SW123 and SW124 short-circuit, the electric charge stored in the first capacitor C120 and the second capacitor C121 are discharged, and the voltages of the capacitors are set to zero volts.
Next, at a timing t1, to apply a voltage corresponding to the data “1” of the least significant bit D0 output from the parallel-serial converter circuit 121 to the first capacitor C120, the switch SW120 is short-circuited for a predetermined amount of time. In other words, the voltage of the first capacitor C120 is set to the first voltage VRT, and an electric charge Ca×VRT is stored in the first capacitor C120.
Then, at a timing t2, the switch SW122 is short-circuited for a predetermined amount of time, and the first capacitor C120 and the second capacitor C121 are connected in parallel. Part of the electric charge stored in the first capacitor C120 is discharged to the second capacitor C121 so as to set the first capacitor C120 and the second capacitor C121 to equal voltage levels.
Since the first capacitor C120 and the second capacitor C121 have the same capacitance Ca, when the switch SW122 is short-circuited, an electric charge CaXVRT/2 is applied from the first capacitor C120 to the second capacitor C121. The voltage levels of the first and second capacitors C120 and C121 are VRT/2.
Next, to apply a voltage signal corresponding to data “1” of a second least significant bit D1 output from the parallel-serial converter circuit 121 to the first capacitor C120 at a timing t3, the switch SW120 is short-circuited for a predetermined amount of time. In other words, the voltage of the first capacitor C120 is set to the first voltage VRT.
Then, at a timing t4, the switch SW122 is short-circuited for a predetermined amount of time, and the first capacitor C120 and the second capacitor C121 are connected in parallel so as to set the first capacitor C120 and the second capacitor C121 to equal voltage levels.
Since the first capacitor C120 and the second capacitor C121 have the same capacitance Ca, when the switch SW122 is short-circuited, an electric charge Ca×VRT/4 is applied from the first capacitor C120 to the second capacitor C121. The voltage levels of the first and second capacitors C120 and C121 are VRT×¾.
Next, to apply a voltage signal corresponding to data “1” of a third least significant bit D2 output from the parallel-serial converter circuit 121 to the first capacitor C120 at a timing t5, the switch SW120 is short-circuited for a predetermined amount of time. In other words, the voltage of the first capacitor C120 is set to the first voltage VRT.
Then, at a timing t6, the switch SW122 is short-circuited for a predetermined amount of time, and the first capacitor C120 and the second capacitor C121 are connected in parallel so as to set the first capacitor C120 and the second capacitor C121 to equal voltage levels.
Since the first capacitor C120 and the second capacitor C121 have the same capacitance Ca, when the switch SW122 is short-circuited, an electric charge Ca×VRT/8 is applied from the first capacitor C120 to the second capacitor C121. The voltage levels of the first and second capacitors C120 and C121 are VRT×⅞.
Next, to apply a voltage signal corresponding to data “1” of a most significant bit D3 output from the parallel-serial converter circuit 121 to the first capacitor C120 at a timing t7, the switch SW120 is short-circuited for a predetermined amount of time. In other words, the voltage of the first capacitor C120 is set to the first voltage VRT.
Then, at a timing t8, the switch SW122 is short-circuited for a predetermined amount of time, and the first capacitor C120 and the second capacitor C121 are connected in parallel so as to set the first capacitor C120 and the second capacitor C121 to equal voltage levels.
Since the first capacitor C120 and the second capacitor C121 have the same capacitance Ca, when the switch SW122 is short-circuited, an electric charge Ca×VRT/16 is applied from the first capacitor C120 to the second capacitor C121. The voltage levels of the first and second capacitors C120 and C121 are VRT× 15/16.
As shown in FIG. 14, when “1010” is input as digital signals D3D2D1D0, the voltage level of the output voltage Vout is maintained at zero volts by the least significant bit D0 output from the parallel-serial converter circuit 121. Then, the voltage level is set to VRT×½ by the subsequent second bit D1, then set to VRT×¼ by the subsequent third bit D2, and then set to VRT×⅝ by the most significant bit D3.
As shown in FIG. 15, when “0101” is input as digital signals D3D2D1D0, the voltage level of the output voltage Vout is set to VRT×½ by the least significant bit D0 output from the parallel-serial converter circuit 121. Then, the voltage level is set to VRT×¼ by the subsequent second bit D1, then set to VRT×⅝ by the subsequent third bit D2, and then set to VRT× 5/16 by the most significant bit D3.
As shown in FIG. 16, when “0000” is input as digital signals D3D2D1D0, the voltage level of the output voltage Vout is not increased and is maintained at zero volts by the least significant bit D0, the second bit D1, the third bit, D2, and the most significant bit D3 output from the parallel-serial converter circuit 121.
In this way, a serial cyclic D/A converter circuit is advantageous in that the circuit size is basically not increased even when the number of bits input as digital data is increased.